Phase change non-volatile memories (ePCMs—embedded Phase Change Memories) may represent a new generation of integrated memories, in which the characteristics of materials having the property of switching between phases with different electrical characteristics are exploited for storing information. These materials may switch between a disorderly amorphous phase and an orderly crystalline or polycrystalline phase. Resistivities with considerably different values, and consequently, a different value of a data stored are associated with the two phases. For example, the elements of the sixth group of the periodic table, such as tellurium (Te), selenium (Se), or antimony (Sb), called chalcogenides or chalcogenic materials, may advantageously be used for phase change memory cells. In particular, an alloy made of germanium (Ge), antimony (Sb), and tellurium (Te), known as GST (having a chemical composition Ge2Sb2Te5), is currently widely used in these memory cells.
Phase changes may be obtained by locally increasing the temperature of the cells of chalcogenic material, through resistive electrodes (generally known as heaters) set in contact with respective regions of chalcogenic material. Access devices (for example metal oxide field effect transistors (MOSFETs)), are connected to the heaters and enable selective flow of an electric programming current through a respective heater. This electric current, by the Joule effect, generates the temperatures for a phase change. In particular, when the chalcogenic material is in the amorphous state, with high resistivity (the “RESET” state), a current/voltage pulse (or an appropriate number of current/voltage pulses) of a duration and amplitude is applied to enable the chalcogenic material to cool slowly. Subjected to this treatment, the chalcogenic material changes its state and switches from the high-resistivity state to a low-resistivity state (the “SET” state). Instead, when the chalcogenic material is in the SET state, a current/voltage pulse of an appropriate duration and a high amplitude is applied to cause the chalcogenic material to return into the high-resistivity amorphous state.
During reading, the state of the chalcogenic material is detected by applying a voltage that is sufficiently low as not to cause a sensible heating thereof, and then by reading the value of the current that flows in the memory cell. Since the current is proportional to the conductivity of the chalcogenic material, it may be possible to determine in which state the material is found, and thus determine the data stored in the memory cell. In general, PCMs allow advantages, among which a high scalability and reading speed combined with a low current consumption and a high efficiency.
In a known manner, and as is shown schematically in FIG. 1, a non-volatile PCM device, designated by 1, generally comprises a memory array 2 made up of a plurality of memory cells 3, organized in rows (wordlines—WL) and columns (bitlines—BL). Each memory cell 3 includes a storage element 3a and an access element 3b connected in series between a respective bitline BL and a reference potential terminal (for example, ground, GND). In particular, a wordline WL is defined by the set of all the control terminals of the access elements 3b aligned along one and the same row.
The storage element 3a includes a phase change material (for example, a chalcogenide, such as GST), and is able to store data in the form of resistance levels associated with the various phases assumed by the material. The access element 3b, in the embodiment illustrated, is an N-channel complementary metal oxide semiconductor (CMOS) transistor having its gate terminal connected to a respective wordline WL, its drain terminal connected to the storage element 3a, and its source terminal connected to the reference potential terminal. The access element 3b is controlled and biased to enable, when selected, the flow of a reading/programming (modify) driving current through the storage element 3a, having an appropriate value during respective reading/programming operations.
A column decoder 4 and a row decoder 5 enable selection, based upon address signals received at the input (generated in a known manner and designated as a whole by AS) of the memory cells 3, and in particular of the corresponding wordlines WL and bitlines BL, each time addressed, enabling biasing thereof to appropriate voltage and current values. The column decoder 4 is moreover advantageously configured to define internally two distinct paths towards the bitlines BL of the memory array 2 each time selected: a reading path to selectively create a conductive path between the bitline BL selected and a sense-amplifier stage 7 to compare the current circulating in the addressed memory cell 3 with a reference current to determine the data stored; and a programming path to selectively create a conductive path between the bitline BL selected and a driving stage 8, which is configured to supply the high currents for generating the changes of state during the programming operations for the Set and Reset states.
In the specific case of PCMs, it is also known that the reading operations, as compared to the programming operations, use sensibly lower values for the biasing voltage applied to the wordlines to enable the desired current flow through the storage element 3a, especially when selector transistors of a MOS type are used (for example, a value of 1.2 V during reading and of 2.8 V during programming). In this regard, memory devices of a known type work with two internally available supply voltages: a first supply voltage Vdd, having a logic value, generally comprised between 1.08 V and 1.32 V, for example 1.2 V; and a second supply voltage Vcc, of a higher value, generally comprised between 3 V and 3.6 V. Inside the memory device, intermediate voltages are moreover generated, for example by level-shifter stages, that are for the programming operations of the memory cells.
As shown schematically in FIG. 2, the memory array 2 is generally organized in a plurality of sectors Sn (n being an integer index ranging from 1 to the total number of sectors), each of which comprises a plurality of memory cells 3. Each sector Sn has a plurality of respective local wordlines (in what follows referred to as sector wordlines WLs), which are distinct from those of the other sectors and are physically connected to the memory cells 3 present in the same sector Sn.
In a known embodiment, the row decoder 5 comprises a global row-predecoder stage 9, which receives at an input the first supply voltage Vdd (hence operating in the low-voltage range, i.e., with voltages not higher than the first supply voltage Vdd) and the address signals AS from an address bus. The global row-predecoder stage 9 generates, based upon the address signals AS, appropriate decoded address signals, which are also of a low-voltage type and are designated as a whole by DAS, common to all the sectors Sn of the memory array 2.
The row decoder 5 has a hierarchical architecture and comprises, for each sector Sn, two distinct circuit stages: a global row decoder stage 10, which receives the decoded address signals DAS and generates a first global wordline signal MWL for the reading operations and a second global wordline signal MWL_MV for the writing (programming/erasing) operations; and a local row decoder stage 12, which is operatively coupled to the global row decoder stage 10 and receives the global wordline signals MWL and MWL_MV and drives in an appropriate way, based upon the signals received at input, the sector wordlines WLs. For this purpose, the local row decoder 12 comprises a plurality of row drivers, not illustrated in FIG. 2, each supplying appropriate biasing signals to respective sector wordlines WLs to implement addressing of the corresponding memory cells.
As described in detail in patent application No. EP-A-2,159,800, having a common assignee with the present application, in a known embodiment, suitable level shifters, not shown in FIG. 2, are present within the global row decoder 10 for raising the voltage of the decoded address signals DAS based upon a regulated voltage Vreg for the programming operations (for example, equal to 2.3 V or 2.8 V, in the case of programming of the Set state and of the Reset state, respectively), and in particular for generation of the second global wordline signal MWL_MV.
The local row decoder 12 creates two distinct paths for biasing the sector wordlines WLs: a first path, selected during the reading operations by the first global wordline signal MWL and operating in the low-voltage range; and a second path, selected during the programming operations by the second global wordline signal MWL_MV and operating in the medium-voltage range (i.e., with voltages of a value comprised between the first supply voltage Vdd and the second supply voltage Vcc).
This row decoder architecture has the advantage, as compared to other known approaches (corresponding to different types of memory devices, for example of a flash type), of taking into account the specific characteristics of the PCMB, in particular with regard to the various voltage levels used in the reading and programming operations. In fact, this row decoder architecture envisages two distinct paths, each optimized for the reading and, respectively, the writing operations. For example, the reading path may advantageously comprise only low-voltage transistors (i.e., ones able to withstand operating voltages that are generally not higher than the first supply voltage Vdd), having a reduced thickness of the gate oxides and a small area occupation. However, the same row decoder architecture is relatively highly complex due to the presence of different hierarchical decoding levels and the different decoding paths in reading and programming, which may entail a corresponding large area occupation (notwithstanding the use of low-voltage transistors for decoding during the reading operations).